`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    15:27:22 07/08/2015 
// Design Name: 
// Module Name:    LatchEXMEM 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module LatchEXMEM(
	input [31:0] salidaALUIn,
	input zeroFlagIn,
	input [31:0] salidaAdderIn,
	input [4:0] salidaMuxIn,
	input [31:0] Data2In,
	input RegWriteIn,
	input PCSrc1In,
	input MemRead1In,
	input [3:0] MemWrite1In,
	input MemToReg1In,
	input [2:0] LoadOp1In,
	input vranch,
	input clk,
	output reg [31:0] salidaALUOut,
	output reg zeroFlagOut,
	output reg [31:0] salidaAdderOut,
	output reg [4:0] salidaMuxOut,
	output reg [31:0] Data2Out,
	output reg RegWriteOut,
	output reg PCSrc1Out,
	output reg MemRead1Out,
	output reg [3:0] MemWrite1Out,
	output reg MemToReg1Out,
	output reg [2:0] LoadOp1Out
    );

always@(negedge clk) begin
	if(vranch) begin
		salidaALUOut = salidaALUIn;
		zeroFlagOut  = zeroFlagIn;
		salidaAdderOut  = salidaAdderIn;
		salidaMuxOut  = salidaMuxIn;
		Data2Out  = Data2In;
		RegWriteOut = 0;
		PCSrc1Out = 0;
		MemRead1Out = MemRead1In;
		MemWrite1Out = 0;
		MemToReg1Out = MemToReg1In;
		LoadOp1Out = LoadOp1In;
	end
	else begin
		salidaALUOut = salidaALUIn;
		zeroFlagOut  = zeroFlagIn;
		salidaAdderOut  = salidaAdderIn;
		salidaMuxOut  = salidaMuxIn;
		Data2Out  = Data2In;
		RegWriteOut = RegWriteIn;
		PCSrc1Out = PCSrc1In;
		MemRead1Out = MemRead1In;
		MemWrite1Out = MemWrite1In;
		MemToReg1Out = MemToReg1In;
		LoadOp1Out = LoadOp1In;
	end
end

endmodule
